VHDL Modelling of Low-Cost Memory Fault Detection Tester
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Abstract
Memory modules are widely used in varies kind of electronics system design. The capacity of the memory modules has increased rapidly since the past few years in order to satisfy the high demand from the end-users. The memory modules’ manufacturers demand more units of automatic test equipment (ATE) to increase the production rate. However, the existing ATE used in the industry to carry out the memory testing is too costly (at least a million dollars per ATE tester). The low-cost memory testers are urgently needed to increase the production rate of the memory module. This has inspired us to design a low-cost memory tester. A low-cost memory fault detection tester with all the major fault detection algorithms that used in industry is modelled using Very High Speed Integrated Circuit Hardware Description Language (VHDL) in this paper to support the need of the low-cost ATE memory tester. The fault detection algorithms modelled are MATS+ (Modified Algorithm Test Sequence), MATS++, March C, March C-, March X, March Y, zero-one and checkerboard scan tests. PERL program is used to analyse the simulation results and a log file will be generated at the end of the memory test. Extensive simulation and experimental test results show that the memory tester modelled covers all the memory test algorithms used in the industry. The low-cost memory fault detection tester designed provides the 100 % fault detection coverage for all memory defects.
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References
N. Mukherjee, W. Or, A. Pogiel and J. Rajski, “High Volume Diagnosis in Memory BIST based on Compressed Failure Data,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 3, pp. 441-453, 2010.
M. Melanie and H. Wunderlich, “BISD: Scan-based Built-in Self-diagnosis,” in Proceedings of the Conference on Design, Automation and Test in Europe, vol. 1, pp. 1243-1248, 2010.
M. Carvalho, P. Bernardi and M. S. Reorda, “Optimized Embedded Memory Diagnosis,” in International Symposium on Design and Diagnostics of Electronic Circuits & Systems, vol. 14, pp. 347-352, 2011.
P. Daniel and R. Chandel, “A Flexible Programmable Memory BIST Architecture,” IETE Journal of Education, vol. 51, pp. 67-74, 2010.
P. Bernardi and L. Ciganda, “An Adaptive Low-Cost Tester Architecture Supporting Embedded Memory Volume Diagnosis,” IEEE Trans. on Instrumentation and Measurement, vol. 61, pp. 1002-1018, 2012.
A. J. V. Goor, Testing Semiconductor Memories: Theory and Practice, John Wiley & Sons, 1998.
W. L. Pang, K. Y. Chan, S. K. Wong and C. S. Tan, “VHDL Modeling of Booth Radix-4 Floating Point Multiplier for VLSI Designer’s Library,” WSEAS Trans. on Systems, vol. 12, pp. 678-688, 2013.
J. H. Meza, S. Ostendorff and H. D. Wuttke, “A Configurable Test-Processor for Board-Level Testing,” in Euromicro Conference on Digital System Design, pp. 22-29, 2016. doi: 10.1109/DSD.2016.81.
I A. Grout, Integrated Circuit Test Engineering, Springer, 2006.
G. Harutyunyan, S. Martirosyan, S. Shoukourian and Y. Zorian, “Memory Physical Aware Multi-Level Fault Diagnosis Flow,” IEEE Trans. on Emerging Topics in Computing, doi: 10.1109/TETC.2018.2789818.
T. Koshy and C. S. Arun, “Diagnostic data detection of faults in RAM using different march algorithms with BIST scheme,” in 2016 International Conference on Emerging Technological Trends (ICETT), Kollam, pp. 1-6, 2016. doi: 10.1109/ICETT.2016.7873754.
A. Johnsen, K. Lundqvist, K. Hänninen, P. Pettersson and M. Torelm, “Experience Report: Evaluating Fault Detection Effectiveness and Resource Efficiency of the Architecture Quality Assurance Framework and Tool,” in 2017 IEEE 28th International Symposium on Software Reliability Engineering (ISSRE), Toulouse, pp. 271-281, 2017. doi: 10.1109/ISSRE.2017.31.