No. 3 VHDL Modelling of Low-Cost Memory Fault Detection Tester

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Quek Wei Chun
Pang Wai Leong
Chan Kah Yoong
Lee It Ee
Chung Gwo Chin

Abstract

Memory modules are widely used in varies kind of electronics system design. The capacity of the memory modules has increased rapidly since the past few years in order to satisfy the high demand from the end-users. The memory modules’ manufacturers demand more units of automatic test equipment (ATE) to increase the production rate. However, the existing ATE used in the industry to carry out the memory testing is too costly (at least a million dollars per ATE tester). The low-cost memory testers are urgently needed to increase the production rate of the memory module. This has inspired us to design a low-cost memory tester. A low-cost memory fault detection tester with all the major fault detection algorithms that used in industry is modelled using Very High Speed Integrated Circuit Hardware Description Language (VHDL) in this paper to support the need of the low-cost ATE memory tester. The fault detection algorithms modelled are MATS+ (Modified Algorithm Test Sequence), MATS++, March C, March C-, March X, March Y, zero-one and checkerboard scan tests. PERL program is used to analyse the simulation results and a log file will be generated at the end of the memory test. Extensive simulation and experimental test results show that the memory tester modelled covers all the memory test algorithms used in the industry. The low-cost memory fault detection tester designed provides the 100 % fault detection coverage for all memory defects.

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References

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