Simulation of Dual-Material Hetero-Double Gate Tunnel Field Effect Transistor (TFET) in Sub-Micron Region Manuscript Received: 15 February 2023, Accepted: 1 April 2023, Published: 15 September 2023, ORCiD: 0000-0001-5614-4909, https://doi.org/10.33093/jetap.2023.5.2.7

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Published: Sep 15, 2023
DOI: https://doi.org/10.33093/jetap.2023.5.2.7
Keywords:
TFET, leakage current, transconductance, simulation

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Chun Fui Tan
Faculty of Information Science and Technology, Multimedia University
Ajay Kumar Singh
Electronics and Communication Engineering, NIIT University, Alwar, Rajasthan, India

Abstract

To meet the performance requirements of low power mobile devices, a device with a high ION/IOFF ratio at low-VDD is needed. TFETs are gaining popularity due to their low subthreshold slope and high transconductance compared to MOSFETs. However, silicon-based TFETs have low on-state current, which limits their use in high-performance applications. To overcome this limitation, using a narrower band gap material like Ge can increase tunneling efficiency at the source side. Additionally, the larger ambipolar current associated with Si-TFETs can be reduced by considering a dual-material hetero-double-gate-dielectric (DM HDG) TFET. The main objective of this research is to propose and characterize a new TFET structure by considering the advantages associated with hetero structure and hetero-gate-dielectric TFETs, which realizes a device with an enhanced ION and a suppressed ambipolar current. The structure was fabricated with the addition of a hetero-dielectric Buried Oxide (BOX) on the doped substrate for the reduction of ambipolar current. We will adopt source-to-gate overlap technique to achieve desired subthreshold slope (SS). All the simulations were done by using 2-D TCAD simulator by Atlas Silvaco. The structure was optimized in terms of (ION/IOFF) and other performance metrics and simulation results were compared with other available structures in the literature.

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Vol. 5 No. 2 (2023): https://doi.org/10.33093/jetap.2023.5.2
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