Integration of Multiplication and Floating-Point Extensions in Risc-V: Design and Synthesis
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Abstract
This project involves the design and implementation of the multiplication (M) and floating point (F) extensions and their integration with the base RV32I processor in forming an RV32IMF processor. The multiplication and division unit (MDU) and floating-point unit (FPU) are designed to support these extensions. The MDU is a single module that handles multiplication and division between combinations of signed and unsigned integers. The FPU design is hierarchical with several submodules, such as the AddSubFPU, MulFPU, and DivFPU modules. The single AddSubFPu module handles addition and subtraction. MulFPU and DivFPU handle the multiplication and division, respectively. Additionally, FPU’s top-level module handles sign-injection instructions. FPU Arithmetic demonstrates high accuracy, with relative error limited to around 0.25%. Performance analysis shows an increase in area and power usage compared to the baseline design, along with improved critical path timing. The processor demonstrates stable operation at various frequencies, with one hundred megahertz offering a favourable balance of performance and efficiency.
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References
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