No. 6. Study of Electrical Performance of Hetero-Dielectric Gate Tunnel Field Effect Transistor (HDG TFET): A Novel Structure for Future Nanotechnology Manuscript Received: 17 January 2022, Accepted: 23 February 2022, Published: 15 March 2022

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Tan Chun Fui
Ajay Kumar Singh
Lim Way Soong


Although, dynamic power in portable mobile devices can be reduced by reducing power supply VDD on the cost of increased leakage current. Therefore, maintaining low leakage current in the device is serious issue for minimizing overall power consumption of the circuit and improving the battery life. The conventional Metal Oxide Field Effect Transistor (MOSFET) requires at least 60 mV of gate voltage for better current drive at room temperature which is difficult to achieve due to thermal limit. This limitation of gate voltage requirement degrades the performance of the device at lower VDD. Tunnel Field Effect Transistor (TFET) is a potential candidate to replace CMOS in deep-submicron region due to its lower subthreshold slope SS (< 60 mV/decade) at room temperature. Steep switching in TFET can extend the supply voltage scaling with improved energy efficiency for both digital and analog applications. Despite those advantages, TFETs are suffering from lower ON current and larger ambipolar current. To overcome these shortcomings, a new structure, known as Hetero-dielectric gate TFET (HDG TFET), has been proposed in the literature. Since, in the absence of the compact analytical model, it is difficult to understand the electrical behaviour of the HDG TFET device, therefore, the present paper presents an analytical model of transconductance parameter of HDG TFET device. The electrical performance analysis of HDG TFET device reflects that on current can be increased considerably by choosing gate material of higher work function near the source region which also suppresses the ambipolar current. It is also observed that a thinner silicon film and larger drain bias result in larger transconductance value.

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Q. Zhang, W. Shao and A. Seabaugh, "Low-subthreshold-swing Tunnel Transistors," IEEE Electron. Device. Lett., vol. 27, no. 4, pp. 297-300, 2006.

W. Y. Choi, B. Park, J. D. Lee and T. K. Liu, "Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec," IEEE Electron. Device. Lett., vol. 28, no. 8, pp. 743-745, 2007.

W. Cao, D. Sarkar, Y. Khatami, J. Kang and K. Banerjee, "Subthreshold-Swing Physics of Tunnel Field-effect Transistors," AIP Adv., vol. 4, no. 6, pp. 067141-1-067141-9, 2014.

K. Narimani, S. Glass, P. Bernardy, N. von den Driesch, Q. T. Zhao and S. Mantl, “Silicon Tunnel FET with Average Subthreshold Slope of 55 mV/dec at Low Drain Currents,” Solid-State Electron., vol. 143, pp.62-68, 2018.

J. Lee, G. Kim and S. Kim, “Effects of Back-Gate Bias on Subthreshold Swing of Tunnel Field-Effect Transistor,” Electron., vol. 8, pp. 1-7, 2019.

B. V. V. Satyanarayana and M. D. Prakash, “Design Analysis of GOS-HEFET on Lower Subthreshold Swing SOI,” Analog Integrated Circ. and Sign. Process., vol. 109, pp. 683–694, 2021.

J. Prateek and P. Vishwa and G. Bahniman, “Dual Metal-Double Gate Tunnel Field Effect Transistor with Mono/Hetero Dielectric Gate Material,” J. Comput. Electron., vol. 14, pp. 537-542, 2015.

P. Chandan, D. Debashish and C. Saurabh, “Approach to Suppress Ambipolar Conduction in Tunnel FET using Dielectric Pocket,” Micro & Nano Lett., vol. 14. pp. 86-90, 2019.

K.N. Priyadarshani, S. Singh and Naugarhiya, “A Dual Metal Double Gate Ge-Pocket TFET (DMG-DG-Ge-Pocket TFET) with Hetero Dielectric: DC & Analog Performance Projections,” Silicon, vol. 14, pp. 1593-1604, 2022.

W. Y. Choi and W. Lee, "Hetero-Gate-Dielectric Tunneling Field-Effect Transistors," IEEE Trans. on Electron. Device., vol. 57, no. 9, pp. 2317-2319, 2010.

W. Y. Choi and H. K. Lee, “Demonstration of Hetero-gate-dielectric Tunneling Field-effect Transistors (HG TFETs),” Nano Convergence, vol. 3, pp. 1-15, 2016.

M. Zare, F. Peyravi and S. E. Hosseini, “Impact of Hetero-Dielectric Ferroelectric Gate Stack on Analog/RF Performance of Tunnel FET,” J. Electr. Mater., vol. 49, pp. 5638–5646, 2020.

B. Lu et al., “Fully Analytical Carrier-Based Charge and Capacitance Model for Hetero-Gate-Dielectric Tunneling Field-Effect Transistors,” IEEE Trans. on Electron. Device., vol. 65, no. 8, pp. 3555-3561, 2018.

K. S. Ajay, C. F. Tan and W. X. T. Wilson, “Threshold Voltage Model for Hetero-gate-dielectric Tunneling Field Effect Transistors”, Int. J. Electr. and Comp. Eng., vol. 10, no. 2, pp. 1764-1771, 2020.

K. S. Ajay, C. F. Tan and W. S. Lim, “Drain Current Model for A Hetero-dielectric Single Gate Tunnel Field Effect Transistor (HDSG TFET),” Int. J. Num. Model. Electron. Netw., Device. and Fields, doi:10.1002/jnm.2980, 2021.

Y. S. Yu and F. Najam, “Compact Current Model of Single Gate/Double-Gate Tunneling Field Effect Transistors,” J. Electron. Eng. Technol., vol. 12, no.5, pp. 2014-2020, 2017.

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